Thalamic
Technology

Compute at the electrode.

Modern invasive BCIs stream raw neural data off the implant and process it outside the body. That architecture worked at a hundred channels. It breaks at ten thousand. Thalamic moves the processing onto the implant itself.

01 — The problem

Channel counts are growing exponentially. Everything downstream is not.

Every electrode adds another stream of wideband data. Moving it all off the implant costs bandwidth the link doesn't have and power the tissue can't absorb — the thermal budget of neural tissue is measured in single-digit milliwatts. The result: systems that record more than they can use, throttled at the interconnect.

10,000+
Channels on next-generation arrays
Gb/s
Raw wideband data at the electrode
single-digit mW
Thermal budget of neural tissue
10×–1000×
On-implant reduction, by output level
02 — The architecture

Every stage that can run on the implant, runs on the implant.

The T-1 takes the wideband signal where it is generated and reduces it in place. Filtering, spike detection, feature extraction and compression run as a fixed-function chain; decoding runs on top of it. What crosses the skull is never the raw waveform.

How far down that chain a system stops is a design decision, and not one we think should be fixed in silicon. The same datapath can hand back detected events, a compressed signal, or a decoded estimate — the right level depends on the application, the link budget and how much of the task belongs on the implant at all.

IN
Wideband
continuous signal from the array
ON CHIP /01
Filter · detect
threshold crossings become events
ON CHIP /02
Feature extract
per-event descriptors, not waveforms
ON CHIP /03
Compress
event coding across channels
ON CHIP /04
Decode
optional, when the task allows
OUT
Telemetry
features, signal or intent
FIG. 03 — THE SIGNAL CHAIN, AND WHAT CROSSES THE SKULL
FIG. 04 — T-1 FLOORPLAN, ENGINEERING RENDER (PLACEHOLDER)
03 — Power

Every microwatt becomes heat in tissue.

Power is not a performance metric here, it is a safety constraint: the implant shares its thermal budget with the cortex around it. That rules out running a general-purpose processor at the electrode, and it rules out moving the raw signal out to one.

The architecture is event-driven end to end. Between spikes there is nothing to compute, and the chain spends nothing computing it — energy is drawn when neurons fire, in proportion to how many fire. Activity, not channel count, sets the power draw.

Design envelope
● Targets, pre-silicon
Power classmW-class, implant-safe
Scalingwith activity, not channel count
Datapathfixed-function, event-driven
Off-implant linkkbit/s-class telemetry

Figures on this page are design targets for a pre-silicon architecture, not measured results.

04 — Scaling

A processing unit per module, not per system.

The T-1 is designed as a tile. One die serves a module of channels; a system is built by placing as many as the array needs, each reducing its own share of the signal locally. Channel count grows by adding dies, so the interconnect off the implant does not have to grow with it.

Today's arrays

Hundreds to low thousands of channels, served by a single processing tile.

1 die
Next-generation arrays

Ten thousand channels and above — tiles placed per module, telemetry unchanged.

N dies
100k-channel systems

The regime the architecture is built for: reduction stays local, and only the reduced output is aggregated.

Modular
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